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By R. M. M. Oberman (auth.)
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Extra info for Counting and Counters
Sample text
This load control circuit consists of a 2: 1 data selector when using D flip-flops as memory elements. This circuit is shown in figure 2-12a. A load signal L s = 1 blocks the data input on gate 3 and enables the contral input via gate 2. A load signal L s = 0 enables the data input of the flip-flop via gate 3 and blocks the counter operation via gate 2. Note that there is no special clear function in figure 2-12a. However, it can easily be realised by introducing a third input on gate 3 of all D flip-flops of the counter.
Lines A and B can determine states 0,1,2, and 3, only. Note that state 2 = 3 - I. The diagram with lines can be extended by a third line C so that another 4 states can be indicated. States 4 to 7 inelusive can be obtained from states 0 to 3 inelusive by reflection of lines A and B in mirror PQ. The situation on line C can be considered as an inverted reflection. The reflected binary code originates from Gray [1] and has been applied in relay 52 COUNTING AND COUNTERS P ±1 o 2 3 4 5 6 7 A ±3 B +7 c Figure 3-1 Q Extension of a 2-bit RB code into a 3-bit code counters[2] [3] and in PCM analog-digital converters by means of cathode ray oscillographs.
This can be used as an alarm or a blocking signal. The practical difficulty with this type of general purpose counter is that it requires more than 16 pins on the package. w x y z ~----r-~--~~--~~-+--~----~~-+--~-----4--~~a Figure 2-19 BlN-BCD counter circuit Up-down counters Binary counters can be designed such that they perform an up-count as weIl as a down-count. This up-down count can be performed in two different ways. (i) The pulse source is single so that a gate circuit is required to switch over from up-count to down-count and vice versa.