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By Jacek Gilewicz, Maciej Pindor, Wojciech Siemaszko
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Example text
3 Cache Hierarchy Organization Over the past decade, we have witnessed phenomenal improvements in process technology. This has led to an increase in the available on-chip transistor budget. This transistor budget resulted in a wave of innovations in microarchitecture, such as prefetching, deep pipelines, more aggressive execution, and of course more cores. The increase in the number of on-chip cores, and the sophistication of each core, place significant demands on the memory system. We need highbandwidth, low-latency, high-capacity, scalable memory systems.
Therefore, many aspects of the memory system design need reconsideration and rethinking. 3 The architect needs to answer several questions. How many cores shall we include? a. homogeneous versus heterogeneous)? How many private caches? How many shared caches? )? In order to answer these questions and achieve a balanced design, there are some factors that the designer must take into account. 1 Technological and usage factors The first factor is the available real estate on-chip. Depending on the intended use or sector targeted by this processor, there will be some area constraints.
This sparkled several innovations such as the victim cache [30] that keeps blocks evicted from a cache at replacement for sometime in case they are referenced again instead of interrogating other caches in the hierarchy of the main memory off-chip. The victim cache is very small in size and hence is fast and fully associative. Because with such aggressive cores, several memory requests can exist simultaneously, the concept of memory level parallelism (MLP) was introduced [12]. MLP is very related to lockup-free memory because it generally is tightly coupled with the number of outstanding cache misses.